Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core
Merged summary
TL;DR - An open-source hardware-software framework enables full float16 training on resource-constrained, single-core RISC-V devices. It roughly halves memory use versus float32 with minimal model-performance degradation.
- Uses standard RISC-V Zfh scalar and Zvfh vector float16 extensions.
- Extends the embedded AIfES framework with hardware-specific training functions and layer freezing for transfer learning.
- Adding Zfh to an RV64GC FPGA softcore costs only 1.15% more LUT6 resources and 0.05% more flip-flops at 175 MHz.
- Describes an architecture for integrating Zvfh into the same RISC-V core.
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Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core
TL;DR - An open-source hardware-software framework enables full float16 training on resource-constrained, single-core RISC-V devices. It roughly halves memory use versus float32 with minimal model-performance degradation.
- Uses standard RISC-V Zfh scalar and Zvfh vector float16 extensions.
- Extends the embedded AIfES framework with hardware-specific training functions and layer freezing for transfer learning.
- Adding Zfh to an RV64GC FPGA softcore costs only 1.15% more LUT6 resources and 0.05% more flip-flops at 175 MHz.
- Describes an architecture for integrating Zvfh into the same RISC-V core.