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Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core

Research Efficiency & Systems

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Merged summary

TL;DR - An open-source hardware-software framework enables full float16 training on resource-constrained, single-core RISC-V devices. It roughly halves memory use versus float32 with minimal model-performance degradation.

  • Uses standard RISC-V Zfh scalar and Zvfh vector float16 extensions.
  • Extends the embedded AIfES framework with hardware-specific training functions and layer freezing for transfer learning.
  • Adding Zfh to an RV64GC FPGA softcore costs only 1.15% more LUT6 resources and 0.05% more flip-flops at 175 MHz.
  • Describes an architecture for integrating Zvfh into the same RISC-V core.

Sources (1)

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core

arXiv cs.AR Benjamin Hubinet, Pierre-Alain Moellic, Olivier Savry, Olivier Potin, Jean-Baptiste Rigaud 2026-07-23 arXiv:2607.21130
Public signals Semantic Scholar citations 0 · Semantic Scholar influential citations 0
Providers: Hugging Face · N/A OpenAlex · N/A Publisher · N/A Semantic Scholar · Citations 0 · Influential citations 0 X · N/A Fetched 2026-07-31 07:00:41.089107 UTC

TL;DR - An open-source hardware-software framework enables full float16 training on resource-constrained, single-core RISC-V devices. It roughly halves memory use versus float32 with minimal model-performance degradation.

  • Uses standard RISC-V Zfh scalar and Zvfh vector float16 extensions.
  • Extends the embedded AIfES framework with hardware-specific training functions and layer freezing for transfer learning.
  • Adding Zfh to an RV64GC FPGA softcore costs only 1.15% more LUT6 resources and 0.05% more flip-flops at 175 MHz.
  • Describes an architecture for integrating Zvfh into the same RISC-V core.
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