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The SpiNNaker2 chip: a many-core platform for flexible and scalable brain-inspired computing

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Merged summary

TL;DR - SpiNNaker2 is a 152-core chip combining conventional deep-learning acceleration with scalable neuromorphic computing. Its low baseline power and event-driven architecture enable efficient exploration of dense, sparse, and brain-inspired workloads on one platform.

  • Delivers up to 4.5 INT8 TOPS or 2.7 INT8 TOPS/W, depending on operating mode.
  • Simulates over 150,000 spiking neurons and 1.8 billion synaptic events per second at a 1 ms time step.
  • Integrates ARM M4F processors, dedicated accelerators, event-routing fabric, Gbit Ethernet, and LPDDR4 support.
  • Consumes less than 250 mW at baseline, supporting efficiency under varying workloads.

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The SpiNNaker2 chip: a many-core platform for flexible and scalable brain-inspired computing

arXiv cs.ET Stefan Scholze, Johannes Partzsch, Sebastian Höppner, Florian Kelber, Andreas Dixius, Marco Stolba, Sirine Arfa, Marc Berthel, Georg Ellguth, Jim Garside, Hector A. Gonzalez, Stephan Hartmann, Thomas Kiel-Hocker, Dongwei Hu, Matthias Jobst, Khaleelulla Khan Nazeer, Tim Langer, Chen Liu, Gengting Liu, Matthias Lohrmann, Mantas Mikaitis, Felix Neumärker, Amirhossein Rostami, Stefan Schiefer, Tilo Schubert, Delong Shang, Bernhard Vogginger, Yexin Yan, Steve Furber, Christian Mayr 2026-07-27 arXiv:2607.24396 doi:10.1109/ojcas.2026.3714974
Public signals OpenAlex citations 0
Providers: Hugging Face · N/A OpenAlex · Citations 0 Publisher · N/A Semantic Scholar · N/A X · N/A Fetched 2026-08-26 14:44:04.234115 UTC

TL;DR - SpiNNaker2 is a 152-core chip combining conventional deep-learning acceleration with scalable neuromorphic computing. Its low baseline power and event-driven architecture enable efficient exploration of dense, sparse, and brain-inspired workloads on one platform.

  • Delivers up to 4.5 INT8 TOPS or 2.7 INT8 TOPS/W, depending on operating mode.
  • Simulates over 150,000 spiking neurons and 1.8 billion synaptic events per second at a 1 ms time step.
  • Integrates ARM M4F processors, dedicated accelerators, event-routing fabric, Gbit Ethernet, and LPDDR4 support.
  • Consumes less than 250 mW at baseline, supporting efficiency under varying workloads.
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