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RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

Research AI for Chip Design

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Overall 68
Content 80
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Merged summary

TL;DR - RTL-Sequencer predicts register-transfer-level circuit timing by converting logic cones into sequences and processing them with linear sequence models. This approach aims to improve scalability and early-stage timing optimization over graph-based methods.

  • Linearizes logic cones using breadth-first traversal.
  • Adds sequence shuffling, bidirectional modeling, and differentiable modeling.
  • Combines graph and sequence representations in a hybrid architecture.
  • Reported experiments show improvements over state-of-the-art baselines.

Sources (1)

RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

arXiv cs.AR Ziyan Guo, Wenji Fang, Wenkai Li, Yuchao Wu, Shang Liu, Zhiyao Xie 2026-07-17 arXiv:2607.15830
Public signals Semantic Scholar citations 0 · Semantic Scholar influential citations 0
Providers: Hugging Face · N/A OpenAlex · N/A Publisher · N/A Semantic Scholar · Citations 0 · Influential citations 0 X · N/A Fetched 2026-08-12 14:35:22.091917 UTC

TL;DR - RTL-Sequencer predicts register-transfer-level circuit timing by converting logic cones into sequences and processing them with linear sequence models. This approach aims to improve scalability and early-stage timing optimization over graph-based methods.

  • Linearizes logic cones using breadth-first traversal.
  • Adds sequence shuffling, bidirectional modeling, and differentiable modeling.
  • Combines graph and sequence representations in a hybrid architecture.
  • Reported experiments show improvements over state-of-the-art baselines.
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