RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
Merged summary
TL;DR - RTL-Sequencer predicts register-transfer-level circuit timing by converting logic cones into sequences and processing them with linear sequence models. This approach aims to improve scalability and early-stage timing optimization over graph-based methods.
- Linearizes logic cones using breadth-first traversal.
- Adds sequence shuffling, bidirectional modeling, and differentiable modeling.
- Combines graph and sequence representations in a hybrid architecture.
- Reported experiments show improvements over state-of-the-art baselines.
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RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
TL;DR - RTL-Sequencer predicts register-transfer-level circuit timing by converting logic cones into sequences and processing them with linear sequence models. This approach aims to improve scalability and early-stage timing optimization over graph-based methods.
- Linearizes logic cones using breadth-first traversal.
- Adds sequence shuffling, bidirectional modeling, and differentiable modeling.
- Combines graph and sequence representations in a hybrid architecture.
- Reported experiments show improvements over state-of-the-art baselines.