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金刚GC3芯片重新定义视频AI算力规则,国产RISC-V高端算力商业化提速

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TL;DR - Chinese firm 中科通量 unveiled 金刚GC3 at CCF Chip 2026, billed as the world's first RISC-V dataflow-architecture chip purpose-built for video AI and AIGC workloads. It signals a strategy of winning on domain-specific efficiency rather than chasing general-purpose GPUs.

  • Architecture: 12-core RISC-V dataflow design at 2.0GHz with no program counter — nodes fire on "data ready," passing intermediate results down the pipeline instead of round-tripping through global memory, targeting the data-movement energy cost that reportedly exceeds compute cost several times over in video processing.
  • Claimed specs: 200 TOPS INT8, 32 TFLOPS FP16, plus 128 channels of 1080p@30fps hardware decode and 64 channels of encode on a single chip.
  • Positioning: deliberately narrow — AIGC video generation, smart-city analytics, industrial vision — with per-watt video processing density, not peak throughput, cited as the differentiator (per SJTU's 冷静文).
  • Open questions raised at the conference itself: compiler tooling, software ecosystem, and large-scale deployment stability for dataflow architectures remain unproven. Figures are vendor/event claims; no independent benchmarks appear in the source.

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金刚GC3芯片重新定义视频AI算力规则,国产RISC-V高端算力商业化提速

雷峰网 (AI科技评论) 2026-08-06
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Providers: Hugging Face · N/A OpenAlex · N/A Publisher · N/A Semantic Scholar · N/A X · N/A Fetched 2026-09-04 14:20:05.998620 UTC

TL;DR - Chinese firm 中科通量 unveiled 金刚GC3 at CCF Chip 2026, billed as the world's first RISC-V dataflow-architecture chip purpose-built for video AI and AIGC workloads. It signals a strategy of winning on domain-specific efficiency rather than chasing general-purpose GPUs.

  • Architecture: 12-core RISC-V dataflow design at 2.0GHz with no program counter — nodes fire on "data ready," passing intermediate results down the pipeline instead of round-tripping through global memory, targeting the data-movement energy cost that reportedly exceeds compute cost several times over in video processing.
  • Claimed specs: 200 TOPS INT8, 32 TFLOPS FP16, plus 128 channels of 1080p@30fps hardware decode and 64 channels of encode on a single chip.
  • Positioning: deliberately narrow — AIGC video generation, smart-city analytics, industrial vision — with per-watt video processing density, not peak throughput, cited as the differentiator (per SJTU's 冷静文).
  • Open questions raised at the conference itself: compiler tooling, software ecosystem, and large-scale deployment stability for dataflow architectures remain unproven. Figures are vendor/event claims; no independent benchmarks appear in the source.
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